我在上午给之前的数字钟添加了设定时间的功能(基于Virtex 5的数字钟(Verilog)),具体是:开发板上有8个拨动开关,其中第一个已用来作为复位信号使用,所以剩下7个开关。因为时钟显示为8位(加上两个冒号),所以利用7个中的3个开关来选择设定哪一位,然后最后4个正好可以用于设定具体的值。
3个选择设定位的开关输入mode信号,4个设定具体值的开关输入setting信号。当mode为零时,时钟处于计时状态,正常计时;当mode为“3'b000”至“3'b110”的任何一种时,进入设定状态,时钟停止计时,依次设定小时的高位、小时的低位、分钟的高位、分钟的低位、秒的高位、秒的低位。小时不能超过24,否则保持原来的值,分钟、秒不能超过59,否则保持原来的值。设定好后,将mode拨回“3'b000”,则时钟在设定好时间的基础上开始跑。
其中的time_occur.v(整个Project下载:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 | `timescale 1ns / 1ps module time_occur( input clk, input clr, input [2:0] mode, input [3:0] setting, output reg [3:0] hour_high, output reg [3:0] hour_low, output reg [3:0] min_high, output reg [3:0] min_low, output reg [3:0] sec_high, output reg [3:0] sec_low ); reg [26:0] counter; reg enable; always @(posedge clk or posedge clr) begin if(clr==1) begin enable <= 0; counter <= 0; end else begin counter <= counter + 1; if(counter == 66666700) begin enable <= 1; counter <= 0; end else enable <= 0; end end always @(posedge clk or posedge clr) begin if(clr==1) begin hour_high <= 0; hour_low <= 0; min_high <= 0; min_low <= 0; sec_high <= 0; sec_low <= 0; end else begin if(enable == 1 && mode == 0) if(sec_low==9) begin if(sec_high==5) begin sec_low<=0; sec_high<=0; if(min_low==9) begin if(min_high==5) begin min_low<=0; min_high<=0; if(hour_low==3&&hour_high==2) begin hour_high<=0; hour_low<=0; end else if(hour_low==9) begin hour_low<=0; hour_high<=hour_high+1; end else hour_low<=hour_low+1; end else begin min_high<=min_high+1; min_low<=0; end end else min_low<=min_low+1; end else begin sec_low<=0; sec_high<=sec_high+1; end end else sec_low<=sec_low+1; else begin case(mode) 3'b000: begin hour_high <= hour_high; hour_low <= hour_low; min_high <= min_high; min_low <= min_low; sec_high <= sec_high; sec_low <= sec_low; end 3'b001: begin if(setting <= 2) hour_high <= setting; else hour_high <= hour_high; hour_low <= hour_low; min_high <= min_high; min_low <= min_low; sec_high <= sec_high; sec_low <= sec_low; end 3'b010: begin hour_high <= hour_high; if(hour_high==2 && setting <= 4) hour_low <= setting; else if(hour_high==1 && setting <= 9) hour_low <= setting; else hour_low <= hour_low; min_high <= min_high; min_low <= min_low; sec_high <= sec_high; sec_low <= sec_low; end 3'b011: begin hour_high <= hour_high; hour_low <= hour_low; if(setting <= 5) min_high <= setting; else min_high <= min_high; min_low <= min_low; sec_high <= sec_high; sec_low <= sec_low; end 3'b100: begin hour_high <= hour_high; hour_low <= hour_low; min_high <= min_high; if(setting <= 9) min_low <= setting; else min_low <= min_low; sec_high <= sec_high; sec_low <= sec_low; end 3'b101: begin hour_high <= hour_high; hour_low <= hour_low; min_high <= min_high; min_low <= min_low; if(setting <= 5) sec_high <= setting; else sec_high <= sec_high; sec_low <= sec_low; end 3'b110: begin hour_high <= hour_high; hour_low <= hour_low; min_high <= min_high; min_low <= min_low; sec_high <= sec_high; if(setting <= 9) sec_low <= setting; else sec_low <= sec_low; end default: begin hour_high <= hour_high; hour_low <= hour_low; min_high <= min_high; min_low <= min_low; sec_high <= sec_high; sec_low <= sec_low; end endcase end end end endmodule |
声明:本文采用 BY-NC-SA 协议进行授权 | 星期九
原创文章转载请注明:转自《数字钟添加设定时间功能》
数字时钟Xilinx完整工程 
好优美的代码曲线。。。
什么东东?一点不明白啊
@yesureadmin, 基于FPGA芯片弄的一个数字钟,很简单的。
不少FPGA的文章啊
@isayme, 最近才有几篇的。贵博不错,都是技术文章,致敬!
初看是以为你在你的博客上面添加了数字时钟的功能呢
@DH, 如果是你首页的那个时钟可以考虑一下,
纯技术文章。。。。
纯野看到了有很多循环语句。
@纯野, 嗯,程序是在满足条件的前提下不断地被时钟信号的上升沿触发。
围观技术文章。。
@软件街小秘, 不是很有技术含量的说,
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