昨晚上我在GENESYS Virtex 5系FPGA开发板(Genesys Virtex®-5 FPGA 开发套件)上实现了数字钟,不过仅有时钟功能,现在不能设定时间,只能在reset后从“00:00:00”开始跑。

下面是Project里的1个文件的代码,更多文件(整个Project,于Xilinx ISE 12.3 Platform)可下载:
time_occur.v:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 | `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Contact: http://www.ninthday.net // Module Name: time_occur ////////////////////////////////////////////////////////////////////////////////// module time_occur( input clk, input clr, output reg [3:0] hour_high, output reg [3:0] hour_low, output reg [3:0] min_high, output reg [3:0] min_low, output reg [3:0] sec_high, output reg [3:0] sec_low ); reg [26:0] counter; reg enable; always @(posedge clk or posedge clr) begin if(clr==1) begin enable <= 0; counter <= 0; end else begin counter <= counter + 1; if(counter == 66666700) begin enable <= 1; counter <= 0; end else enable <= 0; end end always @(posedge clk or posedge clr) begin if(clr==1) begin hour_high <= 0; hour_low <= 0; min_high <= 0; min_low <= 0; sec_high <= 0; sec_low <= 0; end else begin if(enable == 1) if(sec_low==9) begin if(sec_high==5) begin sec_low<=0; sec_high<=0; if(min_low==9) begin if(min_high==5) begin min_low<=0; min_high<=0; if(hour_low==3&&hour_high==2) begin hour_high<=0; hour_low<=0; end else if(hour_low==9) begin hour_low<=0; hour_high<=hour_high+1; end else hour_low<=hour_low+1; end else begin min_high<=min_high+1; min_low<=0; end end else min_low<=min_low+1; end else begin sec_low<=0; sec_high<=sec_high+1; end end else sec_low<=sec_low+1; else begin sec_low <= sec_low; sec_high <= sec_high; min_high <= min_high; min_low <= min_low; hour_high <= hour_high; hour_low <= hour_low; end end end endmodule |
该module是时钟产生模块,其通过一个enable脉冲信号来控制1秒的变化,因为该module的clk是66.6667MHz,所以在产生enable时计数器加至66666700。
声明:本文采用 BY-NC-SA 协议进行授权 | 星期九
原创文章转载请注明:转自《基于Virtex 5的数字钟(Verilog)》
基于Xilinx数字钟 
代码啊代码啊!
还好我当时没有主攻编程!
@狒狒, 其实编程的感觉不错,
很难,表示看不懂
@独立博客排行榜, 贵站做得非常好,祝贵站发展日趋磅礴,服务更多的独立博客。
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